`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:57:41 11/02/2011
// Design Name:   VGAController
// Module Name:   C:/Users/david/Desktop/16bitcpu/VGAController_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGAController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGAController_test;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire VSync;
	wire HSync;
	wire R;
	wire G;
	wire B;

	// Instantiate the Unit Under Test (UUT)
	VGAController uut (
		.clk(clk),
		.reset(reset),
		.VSync(VSync), 
		.HSync(HSync), 
		.R(R), 
		.G(G), 
		.B(B)
	);

	initial begin
		// Initialize Inputs
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		reset = 1;
		#100
		reset=0;
        
		// Add stimulus here

	end
	
	always begin
		#20 clk=~clk;
   end
	
endmodule

